# This file has been generated using RevKit 1.1 (www.revkit.org) # Command Line: # ./tools/bdd_synthesis.py --filename alu_9.pla --realname alu_9.real # Based on the approach proposed in R. Wille and R. Drechsler. BDD-based synthesis of reversible logic for large functions. In Design Automation Conf., pages 270-275, 2009. .version 2.0 .numvars 7 .variables x0 x1 x2 x3 x4 x5 x6 .inputs c0 c1 c2 a b 0 0 .outputs g g g g g g f .constants -----00 .garbage 111111- .begin t2 x0 x5 t3 x1 x3 x5 t3 x0 x3 x5 t2 x2 x6 t3 x0 x3 x6 t3 x2 x3 x6 t2 x6 x5 t3 x4 x5 x6 t1 x6 .end