// This is a SyReC-file describing the register bench of a RISC CPU as specified in [WSG+:2011].
// This file has been taken from RevLib (www.revlib.org). 

module register_bench(in write(1), in reset(1), in dest(3), in data,
                      inout r[8])
  if ( write && !reset ) then
    r[dest] <=> data
  else
    skip
  fi ( write && !reset )
