RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
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Various operations (varops)


A circuit computing various arithmetic and logical operations.


Download: varops_250.src

Circuit Realizations:

Lib. lines gates costs File Pic. Ref. Notes
MCT+MCF 112 633 1361 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 16 bit
MCT+MCF 224 1305 2801 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 32 bit
MCT+MCF 112 633 1361 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines; 16 bit
224 1305 2801 Download realization No picture available   Initial approach (Sect. IV); if-stm. w/ additional lines; 32 bit
MCT+MCF 96 936 2032 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 16 bit
MCT+MCF 192 1928 4176 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 32 bit
MCT+MCF 112 633 1361 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 16 bit
MCT+MCF 224 1305 2801 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 32 bit
MCT+MCF 112 633 1361 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 16 bit
MCT+MCF 224 1305 2801 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 32 bit
MCT+MCF 96 936 2032 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 16 bit
MCT+MCF 192 1928 4176 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 32 bit
 
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