RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
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CPU register bench (cpu_register)


A register bench of a RISC CPU as specified in [WSG+:2011].


Download: cpu_register_247.src

Circuit Realizations:

Lib. lines gates costs File Pic. Ref. Notes
MCT+MCF 167 293 9833 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 16 bit
MCT+MCF 327 565 19641 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines; 32 bit
MCT+MCF 311 580 7560 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines; 16 bit
MCT+MCF 615 1140 15096 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines; 32 bit
MCT+MCF 166 304 9848 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 16 bit
MCT+MCF 326 576 19656 Download realization No picture available WSSD:2013 Line-aware scheme (Sect. V); 32 bit
MCT+MCF 168 325 2217 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 16 bit
MCT+MCF 328 597 3577 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines; 32 bit
MCT+MCF 312 612 2600 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 16 bit
MCT+MCF 616 1172 4760 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines; 32 bit
MCT+MCF 167 336 2232 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 16 bit
MCT+MCF 327 608 3592 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme; 32 bit
 
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