RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
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CPU ALU over 16 bit (cpu_alu_16bit)


An arithmetic-logic unit of a RISC CPU as specified in [WSG+:2011] with a bit-width of 16.


Download: cpu_alu_16bit_242.src

Circuit Realizations:

Lib. lines gates costs File Pic. Ref. Notes
MCT+MCF 404 6237 662531 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/o additional lines
MCT+MCF 2140 9624 31244 Download realization No picture available WSSD:2013 Initial approach (Sect. IV); if-stm. w/ additional lines
MCT+MCF 142 12591 1281717 Download realization No picture available   Line-aware scheme (Sect. V)
MCT+MCF 405 6487 63025 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/o additional lines
MCT+MCF 2141 9628 30208 Download realization No picture available WSSD:2013 Cost-aware scheme (Sect. VI) if-stm. w/ additional lines
MCT+MCF 143 13073 118751 Download realization No picture available WSSD:2013 Cost- & Line-aware scheme
 
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