RevLib is an online resource for benchmarks within the domain of reversible and quantum circuit design
Universitšt Bremen References Cite RevLib Acknowledgements About RevLib
About RevLib


The number of elements integrated within digital circuits grows exponentially, leading to enormous challenges in Computer Aided Design (CAD). Due to this exponential growth physical boundaries will be reached in the near future. Furthermore, power consumption of circuits becomes a major issue. To face these problems the research in the area of reversible logic and its applications in low-power design and quantum computing has become an intensely studied topic.

In the past many researchers have focused on synthesis of reversible logic (see publications) using the different gate libraries including (multiple control) Toffoli gates (MCT), (multiple control) Fredkin gates (MCF), Peres gates (P), and elementary quantum gates (EQ). Several synthesis methods - heuristic as well as exact ones - have been proposed and implemented.

However, most of these approaches are evaluated with limited sets of benchmarks. Due to page limitations many synthesis results are presented only by listing the respective costs but not the concrete circuit realization. This becomes a significant issue, since some authors use their own cost metrics, which makes it hard to decide which realization is better than others. Thus, a complementary comparison of different algorithms with respect to a large set of benchmarks is often not possible.

These issues are faced by RevLib, an online resource for reversible functions and reversible circuits. The motivation behind RevLib is to ease empirical studies in order to improve the evaluation of new approaches by providing an easy access to a large and complementary benchmark database. RevLib provides a benchmark suite of reversible functions, embeddings of irreversible functions (containing constant inputs and gabarge outputs), as well as high level specifications based on the reversible hardware description language (HDL) SyReC. Furthermore, for each function or specification at least one reversible circuit realization is given. These circuits are obtained from exact synthesis approaches, from heuristic synthesis approaches, or from HDL synthesizers.

Using the benchmarks provided at RevLib, the results of (new) synthesis or optimization approaches can be compared to existing realizations. Furthermore, the provided circuits can serve as benchmarks e.g. for the empirical evaluation of verification approaches, testing methods, or similar purposes. Besides that, RevLib is the main file format for RevKit, a public domain toolkit for reversible circuit design.

To fill the database any researcher can submit function specifications and/or circuit realizations to RevLib. Since no widely accepted format for the specification of reversible functions and reversible circuits exists, a standardized file format is proposed.


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